[Python] [ANNOUNCE] MyHDL 0.5 released

This is a fairly "old" project (2003). At that time, MyHDL didn't
yet have conversion to Verilog.

After reviewing the code again, it's clear that it's written in
RTL (register-transfer level) style. This means that the building
blocks are combinatorial, or triggered on clock edges, closely
reflecting an actual implementation. As it is, it's not
convertible to Verilog (see the MyHDL manual for conversion
constraints), but it's close.

To someone with some synthesis experience, it should be fairly
straightforward to make the code synthesizable. I don't expect
that this would make the code more verbose or less clear.
As your interest was apparently triggered by an example, this
tells me that I should put more emphasis on publishing practical
examples, as conversion to Verilog was already introduced some time
ago (beginning of 2004).

Note also that by now, there are designers that use MyHDL in real
projects, showing that you really can use it to go from Python to
an FPGA (or ASIC). Moreover, with development tools such
as Xilinx WebPack (now on Linux also) that start from Verilog,
this can be done using a zero-cost development environment.

Regards,

Jan

Jan,

What do you see as the main advantage for using MyHDL rather than VHDL
for coding up a chip design?

The fact that MyHDL is technically just another Python application.

So it makes all typical Python advantages available to hardware
designers. No need to discuss those in this forum :-). An additional
advantage for this case may be that Python is a "mainstream"
language, while VHDL/Verilog are really niche languages.

Those who agree with the above may still have two questions:
1) is it meaningful?
2) can it be done?

I believe it's meaningful because in my view digital hardware
design can be regarded as just another specialized software
engineering discipline. Of course, things have to be learned,
but it's not more difficult than other application domains.
I should add that this is not the mainstream view of the
hardware design community :-)

I also believe that MyHDL convincingly shows that it can
be done: in other words, that it has all features of a
true HDL. Technically, the principal idea is the use Python
generators to model concurrency. Actually, I have also
tried hard to make it a *better* HDL, and I believe it is :-)

Regards,

Jan

...
I find that even more intersting :-)
Practical examples are great, I'd seen that you'd introduced conversion to
verilog some time back, but it wasn't clear how much was synthesisable. The
example on the website & seeing MU0 description made me really wonder.
After all MU0 is used as a teaching example of how a very minimal CPU can
be constructed.

MU0 itself is not that interesting, but for me the fact MyHDL might be able
to synthesise it *is* interesting. After all, synthesising such a beast
(essentially) directly from python shows to me a very powerful example
which can be built upon.
Hmm... Very interesting :-)

[different post]
For what it's worth, I agree. I've had some limited experience with
compilation to hardware in the past, specifically to asynchronous hardware,
but given you write code that can include loops, conditionals and these can
be translated to FPGA descriptions and then run this for me blurs the
hardware/software distinction. A specific example that looks like software
I'm thinking of is this:
http://www.cs.man.ac.uk/fmethods/projects/AHV-PROJECT/node8.html

(In particularly it's not really that different from Occam)

Maybe I should continue this conversation on the MyHDL list, since I'd be
interested in getting started in this in a simple way. (Mainly because my
work project Kamaelia is designed, to an extent, with hardware constraints
in mind. Implementing some Kamaelia components in MyHDL would be pretty
cool. This might well be possible since we also use generators to model
concurrency.)

Best Regards,


Michael.

I'll try to clarify. Hardware synthesis is a rather "closed" technology,
with several competing, expensive tools and relatively few practicers.
Hopefully this will change, e.g. with development tools like Xilinx ISE.
Mainstream synthesis starts from the RTL (register transfer) level and
is somewhat limited. So you have to learn about its constraints to write
synthesizable code. These are largely independent of the HDL you use.

The primary (and advertized) goal of MyHDL conversion to Verilog is
implementation through synthesis. However, succesful conversion
doesn't provide any guarantee on synthesizability. Indeed, the
convertor's constraints are much less severe than synthesis constraints:
they are defined mainly by restrictions of the target language. For
example, the convertor can convert while loops, even though they are not
(RTL) synthesizable.

In fact I try to keep the convertor as general as possible, so that
it is also possible to convert higher-level code such as test
benches. I may need this as a substitute for co-simulation once
I tackle conversion to VHDL later this year.

In summary, when using MyHDL you still have to learn about synthesis,
just like in Verilog or VHDL.
For examples such as this, you may have to scale down expectations. If
a loop defines behavior that spans multiple clock cycles, you'll have
to describe it as a finite state machine to make it (RTL) synthesizable.
You're welcome!

Jan