Thanks for the feedback - I'll fix those things and resubmit shortly.

File src/pkg/crypto/md5/md5block_arm.s (right):

src/pkg/crypto/md5/md5block_arm.s:78: ADD R(const), R(t0) ; \
On 2013/07/22 18:41:51, rsc wrote:
If you do
ADD $0x######, R(t0)
This generates

    LDR r11, 0xxxx(PC)
    ADD R(t0), R(t0), r11
MOVW $0x######(R(t0)), R(t0)
I imagine that generates the same code but I haven't tried it. There
isn't really any alternative in native instructions anyway since the
constants in question don't fit into an immediate load.
does the linker emit a load of a PC-relative constant into R11 and
then use R11
in the ADD?
If so, is that faster than doing the MOVM.IA.W to load 4 at a time
from farther
Ignoring cache effects, the LDR/MOVW takes one cycle on an ARM A8 (for
instance) whereas the 4 register MOVM/LDM load only takes 2 cycles which
is a win of 2 cycles and 12 bytes of instruction cache.

I did in fact try the ADD version you suggested and it was quite a bit
slower in the benchmarks (I don't have the exact figures any more
though) - it was one of my intermediate versions.

In old and modern ARM MOVM is the same or faster than multiple MOVW s if
you are loading >= 2 registers as far as I know.

src/pkg/crypto/md5/md5block_arm.s:233: TEXT _md5_block_table(SB),7,$-4
On 2013/07/22 18:41:51, rsc wrote:
Please make this (read-only) data. See the masks and shifts tables
used for AES
in ../../runtime/*.s.
OK I'll have a go with that.

In an ideal world one would quad word align the table to minimise the
number of cache lines it uses but I don't think that is possible is it?



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