FAQ

On 6 Lis, 20:29, Russ Cox wrote:
I believe that in the actual ARM machine instruction encoding, .P is a
0 in position 24 while not .P is a 1.

Russ
This is my test code:

TEXT ·PrePost (SB), 7, $0
MOVW 8(R0), R1
MOVW.IB 8(R0), R1
MOVW.IBW 8(R0), R1
MOVW.IA 8(R0), R1
MOVW.IAW 8(R0), R1

MOVD 8(R0), F0
MOVD.IBW 8(R0), F0
MOVD.IA 8(R0), F0

RET

Disassembled after compilation:

Dump of assembler code for function github.com/ziutek/matrix.PrePost:
=> 0x0002f178 <+0>: ldr r1, [r0, #8]
0x0002f17c <+4>: ldr r1, [r0], #-8
0x0002f180 <+8>: ldrt r1, [r0], #-8
0x0002f184 <+12>: ldr r1, [r0, #-8]
0x0002f188 <+16>: ldr r1, [r0, #-8]!
0x0002f18c <+20>: vldr d0, [r0, #8]
0x0002f190 <+24>: ldc 11, cr0, [r0, #8]!
0x0002f194 <+28>: vldr d0, [r0, #8]
0x0002f198 <+32>: add pc, lr, #0
End of assembler dump.

I think that it should look like this:

ldr r1, [r0, #8] // MOVW 8(R0), R1 [P=1,W=0,U=1]
ldr r1, [r0, #8] // MOVW.IB 8(R0), R1 [P=1,W=0,U=1]
ldr r1, [r0, #8]! // MOVW.IBW 8(R0), R1 [P=1,W=1,U=1]
ldr r1, [r0], #8 // MOVW.IA 8(R0), R1 [P=0,W=0,U=1]
ldrt r1, [r0, #8] // MOVW.IAW 8(R0), R1 [P=0,W=1,U=1]

vldr d0, [r0, #8] // MOVD 8(R0), F0 [P=1,W=0,U=1]
vldr d0, [r0, #8]! // MOVD.IBW 8(R0), F0 [P=1,W=1,U=1]
vldr d0, [r0],#8 // MOVD.IA 8(R0), F0 [P=0,W=0,U=1]

I need MOVD.IA to speedup some numerical calculations and I found that
MOVD.IA doesn't set P bit correctly.

After some research I found that 5l, 5c and 5l treats C_PBIT (and
probably C_UBIT) flag in opposite way than 5a. So I am in confusion,
should 5l, 5c and 5l be fixed or 5a...

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