FAQ
So to fix this issue I need to only swap DA <=> IB and IA <=> DB
After this fix my test code:

TEXT ·PrePost (SB), 7, $0
MOVW 8(R0), R1
MOVW.IB 8(R0), R1
MOVW.IBW 8(R0), R1
MOVW.IA 8(R0), R1
MOVW.IAW 8(R0), R1

MOVD 8(R0), F0
MOVD.IBW 8(R0), F0
MOVD.IA 8(R0), F0

RET

disassembles to:

Dump of assembler code for function github.com/ziutek/matrix.PrePost:
=> 0x0002f178 <+0>: 08 10 90 e5 ldr r1, [r0, #8]
0x0002f17c <+4>: 08 10 90 e5 ldr r1, [r0, #8]
0x0002f180 <+8>: 08 10 b0 e5 ldr r1, [r0, #8]!
0x0002f184 <+12>: 08 10 90 e4 ldr r1, [r0], #8
0x0002f188 <+16>: 08 10 b0 e4 ldrt r1, [r0], #8

0x0002f18c <+20>: 02 0b 90 ed vldr d0, [r0, #8]
0x0002f190 <+24>: 02 0b b0 ed ldc 11, cr0, [r0, #8]!
0x0002f194 <+28>: 02 0b 90 ed vldr d0, [r0, #8]

0x0002f198 <+32>: 00 f0 8e e2 add pc, lr, #0
End of assembler dump.

Fixed-point instructions works fine after fix.

You can see problem in VFP code but it isn't real. After a closer
study of the "ARM Architecture
Reference Manual" it became clear that there is no real vldr pre/post
indexed instructions.

This code:

vldr d0, [r0, #8]!
vldr d0, [r0],#8

can't be generated by 5a because it contains pseudo-instructions. And
as they aren't real pre/post indexed instructions they can't speedup
my code :(

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